1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly to an in-situ process for interlevel dielectric formation.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. Typically, a gate oxide is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each transistor being formed, a gate conductor is formed over the gate oxide, and dopant impurities are introduced into the substrate to form source and drain regions. Dielectric spacers may be formed on the sidewalls of the gate conductor, and may aid in the formation of lightly-doped drain (LDD) portions of the source/drain regions. Dielectric spacers may also isolate the gate from the source/drain regions so that a self-aligned silicide, or salicide, process may be performed on the transistor. A salicide process is often used to form lower-resistance contacts to the transistor source, drain and gate regions by providing a metal silicide layer on upper surfaces of these doped silicon regions.
After transistor fabrication, interconnect structures are required to connect the transistors to form a circuit. Interconnects are patterned from conductive layers which are isolated from the transistors and other interconnect layers by dielectric layers. In the high-density integrated circuits currently being fabricated, more than one interconnect level is typically needed. Interconnects which contact the transistor gate, source and/or drain directly, or which extend between closely spaced contact areas are called "local interconnects". Local interconnects are typically used for making connections between gate, source and/or drain regions of neighboring transistors, and are located in the interconnect level closest to the substrate. Because of their relatively short lengths, low resistivity is less critical, and local interconnects may be formed from higher-resistivity metals such as tungsten, or from doped polysilicon and metal silicides. Interconnects which travel longer distances across the circuit are called "global interconnects". Global interconnects are formed in layers further above the substrate than are local interconnects, and are typically formed from low-resistivity metals such as aluminum or, more recently, copper.
Interconnect formation puts several constraints on the interlevel dielectrics which separate interconnect levels. Because interconnects are formed after source/drain impurity distributions are introduced, relatively low interconnect formation temperatures are needed so that dopant redistribution is minimized. In the case of the interconnect level closest to the substrate (typically a local interconnect level), the interlevel dielectric underlying the interconnect level is in contact with portions of the transistors. In this case, it is particularly important that defects in the dielectric which may interact with a transistor to cause hot carrier effects and/or threshold voltage shifts be minimized. These two requirements, low formation temperature and low defect densities, may be in conflict. For example, plasma-enhanced chemical vapor deposition (PECVD) of dielectric layers allows low-temperature deposition (typically about 400.degree. C. or less), but can also result in excess hydrogen incorporation in dielectrics such as silicon dioxide ("oxide") and silicon nitride ("nitride"). Hydrogen in dielectrics is believed to contribute to hot-electron effects in transistors by increasing the density of available trap states which can be occupied by hot electrons injected into a dielectric. Hydrogen diffuses rapidly in oxide, and so can diffuse to Si/oxide interfaces near the transistor channel, where it may disrupt the pre-existing bonds. Although dangling bonds may be terminated with Si--H bond formation, Si--H bonds are weak and can easily be broken by injected hot electrons. In this way, hydrogen may exacerbate hot-electron effects.
Another desired characteristic for interlevel dielectrics used in interconnect formation is conformality, such that film thickness is equal over all substrate topography. Conformal interlevel dielectrics ensure that an adequate insulator thickness exists under each interconnect conductor for its entire path across the circuit, and minimize the possibility of, for example, void formation in dielectric layers going over steps. In order to maintain adequate insulator thicknesses over higher-lying features even after planarization of a dielectric, interlevel dielectric layers are often made relatively thick (a micron or more). In order to etch via holes through these thick layers to form contacts to the underlying devices or interconnects, a rapid etch process is used. Because etches for dielectrics are generally not perfectly selective over silicon, an etch stop layer may be needed between the substrate and the overlying interlevel dielectric. In this case, it follows that an additional requirement is compatibility between the etch stop and interlevel dielectric layers. Furthermore, it would be desirable that deposition times for the interlevel dielectric and etch stop layers be as short as possible.
It would therefore be of benefit to develop a method for forming a conformal interlevel dielectric for interconnect formation during integrated circuit fabrication. An etch stop layer should be included to prevent overetching of the underlying transistors. The interlevel dielectric should be formed at low temperatures so that redistribution of dopants in the transistors is avoided. The dielectric should also have low hydrogen content, and deposition times should be short.